1. Field of the Invention
This invention relates generally to SMP architectures, and more particularly to stopping a CPU in a SMP architecture.
2. Description of Related Art
Symmetric multiprocessor (SMP) systems are known to those of skill in the art. In general, a multiprocessor system is characterized as symmetric if all processors in the system have the same memory subsystem. Thus, typically, a SMP system 100 includes a plurality of central processing units (CPUs) 101-1 to 101-n connected to a common memory controller 130 and system memory 135 via a common bus 110. Other elements connected to common bus 110 include L2 caches 102-1 to 102-n, a network interface 115, I/O components 116, and a system clock 117.
Various aspects of SMP systems have been considered in the prior art. Some of the SMP system prior art focuses on detecting a CPU failure in SMP system 100 and continuing operations with the failed CPU. See for example, U.S. Pat. No. 5,815,651, entitled “Method and Apparatus For CPU Failure Recovery in Symmetric Multi-Processing Systems,” of Litt, or U.S. Pat. No. 5,583,987, entitled “Method and Apparatus For Initializing A Multiprocessor System while Resetting Defective CPU's Detected During Operation Thereof,” of Kobayashi et al., both of which are incorporated herein by reference.
Other SMP literature concerns determining performance of SMP system 100. See for example, U.S. Pat. No. 5,838,976, entitled “System and Method for Profiling Code on Symmetric Multiprocessor Architectures,” of Summers, which is incorporated herein by reference.
Other aspects in the SMP prior art include U.S. Pat. No. 5,860,002 entitled “System for Assigning Boot Strap Processor in Symmetric Multiprocessor Computer with Watchdog Reassignment,” of Huang, and U.S. Pat. No. 5,860,101, entitled “Scalable Symmetric Multiprocessor Data-Processing System with Data Allocation Among Private Caches and Segments of System Memory,” of Arimillli et al., both of which are incorporated herein by reference.
U.S. Pat. No. 4,394,727, entitled “Multi-Processor Task Dispatching Apparatus,” of Hoffman et al. taught:
. . . task handling apparatus for a multiprocessor computer system where the tasks are distributed to the available processors. Each task is dispatched on the first available processor that can accept it. The signal dispatcher determines which processor is eligible to execute a higher priority task than is being currently executed by that processor. The signal dispatcher signals the eligible processor to activate its task dispatcher. The task dispatcher in the eligible processor performs the task switch and determines which task is to be dispatched. The processor performing the task switch runs its signal dispatcher to determine if the task it had been performing should be run by some other processor. When the processor which is running its signal dispatcher is the processor to do the task switch, it leaves the signal dispatcher cycles and switches to task dispatching cycles without any signaling taking place.
U.S. Pat. No. 4,394,727, Col. 17, lines 17 to 33.